D Flip Flop Verilog Sample Code in Just 10 Lines

Verilog D Flip Flop

This D Flip Flop Verilog program, assigns d (input) to q(output) on each rising edge of the input clock.

module first_v(clk,d,q);
	input clk;
   input d;
   output q;
	reg q; //output reg q;
	always @(posedge clk)
		begin
		q<=d;
	end
endmodule

In the above code, we declare an input signal as our clock input and an input as our “d” input. And in the fourth line, we declare an output as “q”. And we assign the input to output on each rising-edge of the clock.

download files here.

Also, don’t forget to checkout our VHDL Complete Projects Pack here.

Leave a Reply

Your email address will not be published. Required fields are marked *