Verilog Frequency Meter Sample Project

In this Verilog Frequency Meter project, the clock is assumed 3200Hz. By increasing the input clock, higher frequencies can be measured.
This program is made of various parts:

1. Counter.v block: this block counts the input pulses in every second. In this block, there is 2 “Always” that one of them measure 1 second timing and another one counts pulses. At the end of every second, a flag that called RDY becomes ‘1’ and the next block reads measured frequency when this flag becomes ‘1’.
2. Breakup.v block: this block starts working when RDY is ‘1’ and separates the ones, tens, hundreds and thousands and transfer them to next block.
3. S_S.v block: this block receives ones, tens, hundreds and thousands from previous block and displays them on the seven-segments.
4. Top.v block: this block connects these 3 blocks together.

download the project files here.

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