Welcome to the best archive of VHDL Projects. All of these VHDL Projects are ready to use/simulation. You can easily use them in your projects to save your time and accelerate your projects.
Also, don’t forget to checkout our Ultimate DSP Tutorial.
In this program, you should feed the input with 3.2KHz clock frequency so the clock period is 312.5ms. The input voltage pulse inverts every 156.25ms so this program generates 1Hz frequency. You can see the results in the below figure (the simulation of the VHDL code in the Xilinx ISE software). Have any questions? Ask in the comments.
In this program, you should feed the input with 3.2KHz frequency. And for refreshing these 4 seven-segments, the program divides 3.2KHz by 4 (equal to 800Hz) and if each 7-segments
In the above figure, the input frequency is 500Hz. In this program, the input frequency is 3.2KHz. This project is made of three main processes. The second process by receiving every rising-edge of the desired frequency, due to the value of r signal, it either sets the frequency counter to zero or reads frequency counter value and or increases the frequency by 1.
How it Works?
The first process by receiving every 16 input-clock pulses, increases c by 1 and when c became 3, increases q by 1. when q became 51 (3200Hz = 51 x 4 x 16), the variable r becomes 2 and then the second process reads the frequency and when q became 52, r becomes 1 to frequency becomes 0 again.
The third process separates the ones and tens and hundreds and thousands of the measured frequency and because this project have only four seven-segments, only frequencies that are less than 9999Hz can be measured.
In this program, an internal FPGA FIFO buffer that is created by Core Generator is used. FIFO stands for First In First Out and it is a kind of RAM that used for storing data. These memories are useful in implementing communication protocols like USB, UART and PCI-Express. In this program, “din” and “dout” are data input and data output, respectively and “ren” and “wen” are write enable and read enable, respectively and “wclk” and “rclk” are write clock and read clock, respectively and “full” specifies the state of FIFO being full.
This program receives the data from the UART protocol and assigns them on 8-bit parallel output.
The UART protocol in idle state has 5-volts on its TX and RX pins. And when the transmission beings, first the TX line becomes low for a certain period of time and then, data transmission starts and after sending 8 bits of data, the stop bit which is 5 volts, is sent. So again, it goes to the idle state (or a new start begins). In this program, the baud-rate is 9600 it means 9600bps (bit per second) and each bit takes around 104uS. You should feed the input with a 50MHz clock. So, a counter counts to 5200 to generate the 104uS timing. In this program a state machine algorithm is used to switch between start, data, stop, w and idle states according to the input pulses.
This program is made of two sections. One of them is the above program (S2P_Bridge) and another one is a FIFO Buffer that is used as a Core. The functional side of this program is that the data from the output of S2P_Bridge stored in the FIFO and whenever we want, we can read it. In this case, we don’t lose data.
This project can recognize a pattern of pulses (for example a passcode). If the input stays high for 3mS and then stays low for 1ms and then stays high for 2ms and then stays low, the output stays high for 1s and if before the 1s is ended this pattern received, the output stays high for 1ms more. In this program the input frequency is 50MHz. The below figure describes the 3 main modules of this program.
In the above figure build_1ms generates 1ms timing for Build_1s block to set output to high state after 1ms. The recognize_pulse block detects the input pulses pattern and by receiving that specific pattern, sends a signal to Build_1s block. Then, this block sets its output to high state.
In this program, the input frequency is 50MHz and it is divided by 2, 4, 8, 16, 32, 64, 128, and 256 and due to the state of the dip-switch, it assigns one of the divided frequencies to the output.
This program is made of 2 processes. In the first process, when its counter reached 1 million, it reads the state of buttons and according to the pushed button, it changes the value of count2 and count3. And the second process generates PWM with dynamic duty cycle according to count2 and count3.
Modern communication protocols use differential IO because it is better for long range data transmission and reduces the noise. Almost all of the FPGA pins support differential mode. The unisim library is used to configure pins to the differential mode and Portmap is used to assign inputs and output. In this program, the differential pins are configured as input. It converts signals from the pair of differential pins to a normal output pin. Also, the output pins can be configured as differential pins (OBUF). We use normal signals inside the program but at the end we connect them to differential pins in the top file.
This program is made of multiple state-machines.
- After sending each command, we should wait until LCD execute that command (according to the busy pin) and then we send the next command.
- Init: in this state, the program sends the h38 code to configure the LCD in 8bit mode.
- Ond: in this state, the program sends the h0F code to turn on the LCD.
- Cls: in this state, the program sends the h01 code to clear pixels on the LCD.
- Sd: in this state, the program displays a number (number ‘0’ ASCII = h30) on the LCD.
In this program, the input frequency is 50MHz and the baud-rate of UART is 9600 (104us per bit). Every 5208 clock pulse is equal to 104us. When the program receives data from UART, it rises the RDY flag, and when the LCD driver receives the RDY flag signal, it sends the input data to the LCD. In this program, there is a separate program that sends the time between received data to the PC by using tx_time and uart_t files. These two programs are completely separate from each other and they run simultaneously. The state machine of the LCD driver has two more states which one of them is for switching to the next line of the LCD and another one is for clearing the LCD and returning the cursor to the default position.
The hardware receives 32 bytes (after receiving 1 more byte, it goes to the second line of the display) and sends them to be displayed on the LCD and after that, because the LCD becomes full, it clears the LCD and returns the cursor to the default position.
The below figure is the pinout of female ps2 port (on the computer).
The standard key codes are like the following figure.
(some keys have wrong code in the above figure)
Scanning the keyboard keys is like UART protocol and the data transmission timing is like the following figure.
By clicking each key, the KB sends data + CLK, so the FPGA reads the data line on the falling-edge of CLK. When the keyboard is not sending any data, the data pin in both keyboard and FPGA is in input mode. So, for a reliable data transmission, a pullup resistor is necessary for both data and clock lines. When the FPGA hold clock pin in zero state, then the keyboard store all pushed keys to its internal FIFO. And when the FPGA release the clock pin, the keyboard transmits the pushed keys codes to the FPGA.
The Big Problem
The big problem is that the keyboard keys codes aren’t ASCII codes so a we designed a data convertor block (rd_kbd.vhd) that has a 256 member const (k_code_l) that contains the codes but it only works for small letters. Actually, this const is implemented by look up tables. This block contains a state machine with below states.
- Free: In this state, it waits until the line isn’t free (the clock and data lines are ‘0’).
- Wpk: This state is the idle state and the program stays in this state until the clock pin becomes ‘0’.
- Cl: The program stays in this state while the clock line is ‘0’.
- Ch: The program stays in this state while the clock line is ‘1’.
- Rd: The program enters this state on the falling-edge of the clock. In this state when the data isn’t received completely, it stores bits and goes back to state 3 until the next falling-edge of clock. But if the data is received completely, it converts the received data to ASCII and rises the RDY flag and the LCD hardware displays the data on the LCD. (ESC key clears the LCD texts)
In this program, the input frequency is 50MHz but it uses a DCM block to generate a 110MHz to display a 1440×900 80fps frame through the VGA port.
106MHz = 80 900×1440
But the output of the DCM block is 110MHz so the frame rate is about, 85fps. The colored rectangle can be moved by two push buttons. The VGA port protocol is designed for CRT monitors but also new LED monitors uses that standard too and for receiving the frame data, the data is converted to a digital and modern protocol inside of them for the display. In this example our display is made of 1440 Columns and 900 rows.
VSYNC and HSYNC
The control signals: First the Hsync signal is ‘1’ and Vsync is ‘0’ to move the ray to right to scan the first line of the display and after Hsync is ‘0’ to return the ray to the first of the second line (the ray pointer needs a specific time to return) and after a spcific timing the Hsync becomes ‘1’ and this process runs 900 times per frame to scan each line of the display. After scanning all of the lines, Vsync is ‘1’ to return the ray to the first line (the ray pointer needs a specific time to return). This process should run 80 times per second (80fps). By calculating the return timings, Hsync should counts to 1903 and Vsync to 931 and when the Hsync reaches 1440 and Vsync 900, the ray should be turns off.
How Colors are Converted to Analog wave?
In this program, 2 pins are used for blue color and 2 pins for red and 3 pins for green (128 colors = 4 blue X 4 red X 8 green). The VGA connector have 15 pins that 3 of them are for RGB and 2 of them are for sync signals (Hsync and Vsync) and others are GND or unused.
For converting digital color signals to analog, just a few resistors are needed As shown in the figure below.
In the above figure, the R2 resistance is half of R1 resistance.
Obviously, the larger the number of blue pins (for example, 8 pins), the more colors can be created. As shown in the figure below.
The resistance of the resistors must be half of their previous resistor. For example, if R1 is 20K, R2 must be 10K and R3 must be 5K. Actually, this is a simple DAC (Digital to Analog Converter) circuit that is useful in low resolution systems.
This program displays a rectangle on VGA port and receives data from UART to display it on Char LCD and sends time to PC by UART and generates a PWM wave. These programs run parallelly without affecting each other.
This program uses 2 counters that one of them is Wr_index and another one is Rd_index. Rd_index points to the location that user wants to read and Wr_index points to the location that user wants to write in it. By every write operation the Wr_counter increases and when the Wr_index reaches the maximum value (in this program, the default FIFO size is 16 bytes that can be changed by user before synthesis), it means that the FIFO is full and the “Full” signal becomes ‘1’ and by every read operation, the counter value decreases until the FIFO becomes empty and then the “empty” signal will becomes ‘1’. The purpose of writing this program is to deeply understand the FIFO memory.
Ram has 2 modes that are “single” and “dual”. In the “single” mode, the ram can be either read or written. But in the “dual” mode, the Ram can be written and read simultaneously. They are also called single rams and dual rams, respectively. When the DIR pin is ‘1’ the data can be read and when it is ‘0’, the data can be written into the ram. The read and write operations are possible only when the “EN” signal is ‘1’ otherwise the bus goes to Hi-Z state.
This program uses a state machine in order to sort numbers in only 3 clock cycles. In the first cycle, the input numbers are compared in pairs and the larger numbers will be selected and in the second cycle of the clock, the selected larger numbers and the selected smaller numbers are compared to each other in pairs and in the third clock, the final result is ready.
The internal multiplier of the FPGA can multiply two 18bit numbers with a 36bit output. For testing this multiplier, we should give it random numbers and watch the output to make sure it is ok. We can also use the Textio tool to save the given numbers and the results to a text file.
Sometimes developers need to implement a logic circuit multiple times in their programs. They copy and paste the same code multiple times and waste their time. But they don’t need to do this. They can write them as a function and use them hundreds of times without rewriting them. By using functions, the program looks clean and organized.
For creating FIR filter using Core, some factors are needed that we can calculate these factors using the Matlab software (just need to open FDA Tool by typing it in the Matlab terminal).